EEPROM devices are well known memory devices which are used for non-volatile storage of data. CMOS EEPROM devices are particularly adapted for use where power consumption is critical. For example, in battery powered applications, as the power consumption of a device decreases, its usefulness increases.
During operation, EEPROM devices generate a plurality of signals having a variety of voltage levels. One type of EEPROM device, referred to as a "thick-oxide" EEPROM incorporates a three layer polysilicon structure as the individual bit memory element. The three layers of polysilicon are separated from each other by a layer of oxide so that the second layer is electrically insulated from the other two. Data is retained on the second layer, which is sometimes referred to as the "floating gate." Data is stored on the floating gate by placing a high programming voltage (in the range of 25 volts) on a programming electrode so that electrons tunnel across the insulating oxide layer from the programming electrode and are trapped on the floating gate. Data is erased from the floating gate by placing a sufficient voltage across the floating gate to force the electrons on the floating gate to tunnel across a second oxide layer from the floating gate to an erase electrode.
Virtually all memory devices consist of a plurality of bit memory cells organized in an array of columns and rows. Individual cells are selected by decoder circuitry which generates the appropriate signals to address the proper row and column to access a desired cell or group of cells. The control lines associated with particular rows and columns of the memory are typically referred to as select lines.
In CMOS EEPROM devices, it is desirable to control the voltage on the select lines as closely as possible. Since the memory cells employ a "floating gate" for memory retention, it is essential that known voltages be present on the other portions of the cell so that the magnitude of the charge on the floating gate can be referenced to some known voltage. Therefore, in an EEPROM device, some means are required to regulate or limit the voltage on the memory cell select lines. This problem is complicated by the fact that EEPROM devices present largely capacitive loads and abnormal voltages may be generated due to voltage overshoot during the operation of the device.
This problem has been addressed in prior devices by coupling voltage clamping circuits to the select lines (among others) in EEPROM devices to regulate critical voltages for predictable EEPROM operation. Prior voltage clamping circuits have relied on complicated circuit topologies using comparators and other components which consume a relatively large amount of current. It can be shown that the amount of current required by a voltage clamping circuit is directly related to the number of devices used in the circuit as well as the method used to sense the voltage to be clamped. For example, in one prior voltage clamping technique, a string of series connected diodes, operating above device threshold, is used to clamp the regulated voltage. Thus, this clamping circuit consumes current by maintaining the string of diodes in a forward biased condition. The present invention overcomes high current consumption by providing a voltage sensing circuit with negative feedback which supplies current to the diode string in levels which correspond to sub-threshold operating regions of the voltage clamping diodes, thus providing a substantial reduction in current consumption over prior devices. In addition, the present voltage clamping circuit achieves this result with substantially fewer components than prior clamp circuits, thus providing a substantial reduction in current drain and a substantial improvement in reliability over prior voltage clamping circuits.
Clamping a negative voltge is also useful in CMOS EEPROM devices which require negative reference voltages for accurate cell programming. The present invention provides a voltage clamping circuit wherein a negative reference voltage may be generated without altering the negative power source. Since the generation of a negative voltage typically involves a voltage regulator which consumes current, it is desirable to minimize the current demands on the negative power source. The present invention therefore provides a stable negative reference voltage while requiring an extremely small amount of current from the negative power source. It also enables operation with supply voltages which produce large variations in the negative voltage generated by the on-chip V.sub.BB generator.